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    SubjectRe: [generalized cache events] Re: [PATCH 1/1] perf tools: Add missing user space support for config1/config2
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    On Fri, 2011-04-22 at 09:51 -0700, Andi Kleen wrote:
    >
    > Micro architectures are so different. I suspect a "generic" definition would
    > need to be so vague as to be useless.
    >
    > This in general seems to be the problem of the current cache events.
    >
    > Overall for any interesting analysis you need to go CPU specific.
    > Abstracted performance analysis is a contradiction in terms.

    It might help if you'd talk to your own research department before
    making statements like that, they make you look silly.

    Intel research has shown that you don't actually need exact definitions
    as a side effect of applying machine learning principles in order to
    provide machine aided optimizing (ie. clippy style guides for vtune).

    They create simple micro-kernels (not our kind of kernels, but more like
    the excellent example Arun provided) that trigger a pathological case
    and a perfect counter-case and run it over _all_ possible events and do
    correlation analysis.

    The explicit example given was branch misses on an atom, and they found
    (to nobody's great surprise) BR_INST_RETIRED.MISPRED to be the best
    correlating event. But that's not the important part.

    The important part is that all it needs is a strong correlation, and it
    could even be a combination of events, it would just make the analysis a
    bit more complex.

    Anyway, given a sufficient large set of these pathological cases, you
    can train a neural net for your target hardware and then reverse the
    situation, run it over an unknown program and have it create suggestions
    -> yay clippy!

    So given a set of pathological cases and hardware with decent PMU
    coverage you can train this thing and get useful results. Exact event
    definitions be damned -- it doesn't care.

    http://sites.google.com/site/fhpm2010/program/baugh_fhpm2010.pptx?attredirects=0


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