Messages in this thread Patch in this message | | | From | Tejun Heo <> | Subject | [PATCH 2/4] x86-32: Increment SECTION_SIZE_BITS to 30 when X86_PAE | Date | Thu, 31 Mar 2011 20:02:44 +0200 |
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When X86_PAE is enabled, SECTION_SIZE_BITS is 29 and MAX_PHYSADDR_BITS 36 making SECTIONS_WIDTH 7, which is different from !X86_PAE case where the width is 6. On x86, when all the related options are enabled, NR_PAGEFLAGS reaches 26 and thus can accomodate only 6 more bits, not 7.
This direcrepancy leads to confusing Kconfig restrictions like disabling of ARCH_SUPPORTS_MEMORY_FAILURE depending on combinations of options.
This patch bumps SECTION_SIZE_BITS to 30 when X86_PAE. This change increases sparse memory model granuality from 512MiB to 1GiB which in turn can increase the amount of wasted memory in memmap when the memory sections aren't aligned. The amount of wastage can be a few MiB per unaligned section.
Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Yinghai Lu <yinghai@kernel.org> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Thomas Gleixner <tglx@linutronix.de> --- arch/x86/include/asm/sparsemem.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/x86/include/asm/sparsemem.h b/arch/x86/include/asm/sparsemem.h index 4517d6b..71b8671 100644 --- a/arch/x86/include/asm/sparsemem.h +++ b/arch/x86/include/asm/sparsemem.h @@ -16,7 +16,7 @@ #ifdef CONFIG_X86_32 # ifdef CONFIG_X86_PAE -# define SECTION_SIZE_BITS 29 +# define SECTION_SIZE_BITS 30 # define MAX_PHYSADDR_BITS 36 # define MAX_PHYSMEM_BITS 36 # else -- 1.7.1
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