Messages in this thread | | | Date | Thu, 03 Mar 2011 14:27:54 +0900 | From | Masami Hiramatsu <> | Subject | Re: [RFC PATCH] x86: stop machine text poke should issue sync core |
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(2011/03/01 0:24), Mathieu Desnoyers wrote: > Intel Archiecture Software Developer's Manual section 7.1.3 specifies that a > core serializing instruction such as "cpuid" should be executed on _each_ core > before the new instruction is made visible. > > Failure to do so can lead to unspecified behavior (Intel XMC erratas include > General Protection Fault in the list), so we should avoid this at all cost. > > This problem can affect modified code executed by interrupt handlers after > interrupt are re-enabled at the end of stop_machine, because no core serializing > instruction is executed between the code modification and the moment interrupts > are reenabled. > > Because stop_machine_text_poke performs the text modification from the first CPU > decrementing stop_machine_first, modified code executed in thread context is > also affected by this problem. To explain why, we have to split the CPUs in two > categories: the CPU that initiates the text modification (calls text_poke_smp) > and all the others. The scheduler, executed on all other CPUs after > stop_machine, issues an "iret" core serializing instruction, and therefore > handles core serialization for all these CPUs. However, the text modification > initiator can continue its execution on the same thread and access the modified > text without any scheduler call. Given that the CPU that initiates the code > modification is not guaranteed to be the one actually performing the code > modification, it falls into the XMC errata.
Thanks Mathieu! It seems reasonable change. At least I'm OK :)
Reviewed-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
> > Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> > CC: Peter Zijlstra <peterz@infradead.org> > CC: Arjan van de Ven <arjan@infradead.org> > CC: "H. Peter Anvin" <hpa@zytor.com> > CC: Thomas Gleixner <tglx@linutronix.de> > CC: Steven Rostedt <rostedt@goodmis.org> > CC: Ingo Molnar <mingo@elte.hu> > CC: Andrew Morton <akpm@linux-foundation.org> > CC: Andi Kleen <andi@firstfloor.org> > CC: Frederic Weisbecker <fweisbec@gmail.com> > CC: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> > --- > arch/x86/kernel/alternative.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > Index: linux-2.6-lttng/arch/x86/kernel/alternative.c > =================================================================== > --- linux-2.6-lttng.orig/arch/x86/kernel/alternative.c > +++ linux-2.6-lttng/arch/x86/kernel/alternative.c > @@ -612,6 +612,12 @@ static int __kprobes stop_machine_text_p > > flush_icache_range((unsigned long)tpp->addr, > (unsigned long)tpp->addr + tpp->len); > + /* > + * Intel Archiecture Software Developer's Manual section 7.1.3 specifies > + * that a core serializing instruction such as "cpuid" should be > + * executed on _each_ core before the new instruction is made visible. > + */ > + sync_core(); > return 0; > } >
-- Masami HIRAMATSU 2nd Dept. Linux Technology Center Hitachi, Ltd., Systems Development Laboratory E-mail: masami.hiramatsu.pt@hitachi.com
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