Messages in this thread | | | Date | Sat, 26 Mar 2011 12:08:47 +0000 | From | Alan Cox <> | Subject | Re: advice sought: practicality of SMP cache coherency implemented in assembler (and a hardware detect line) |
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> Probably not. Is it a virtual or physical indexed cache? Do you have a > precise workload in mind? If you have a very precise workload and you > don't expect to get many write conflicts then it could be made to > work.
I'm unconvinced. The user space isn't the hard bit - little user memory is shared writable, the kernel data structures on the other hand, especially in the RCU realm are going to be interesting.
> There are a number of mature cores out there that can do this already > and can be bought off the shelf, I wouldn't underestimate the > difficulty of getting your cache coherency protocol right particularly > on a limited time/resource budget.
Architecturally you may want to look at running one kernel per device (remembering that you can share the non writable kernel pages between different instances a bit if you are careful) - and in theory certain remote mappings.
Basically it would become a cluster with a very very fast "page transfer" operation for moving data between nodes.
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