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    Subject[05/70] drm/radeon/kms: fix interlaced modes on dce4+
    2.6.37-stable review patch.  If anyone has any objections, please let us know.

    ------------------

    From: Alex Deucher <alexdeucher@gmail.com>

    commit c9417bdd4c6b1b92a21608c07e83afa419c7bb62 upstream.

    - set scaler table clears the interleave bit, need to
    reset it in encoder quirks, this was already done for
    pre-dce4.
    - remove the interleave settings from set_base() functions
    this is now handled in the encoder quirks functions, and
    isn't technically part of the display base setup.
    - rename evergreen_do_set_base() to dce4_do_set_base() since
    it's used on both evergreen and NI asics.

    Fixes:
    https://bugzilla.kernel.org/show_bug.cgi?id=28182

    Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
    Signed-off-by: Dave Airlie <airlied@redhat.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

    ---
    drivers/gpu/drm/radeon/atombios_crtc.c | 22 +++++-----------------
    drivers/gpu/drm/radeon/radeon_encoders.c | 20 +++++++++++++++-----
    2 files changed, 20 insertions(+), 22 deletions(-)

    --- a/drivers/gpu/drm/radeon/atombios_crtc.c
    +++ b/drivers/gpu/drm/radeon/atombios_crtc.c
    @@ -959,9 +959,9 @@ static void atombios_crtc_set_pll(struct
    }
    }

    -static int evergreen_crtc_do_set_base(struct drm_crtc *crtc,
    - struct drm_framebuffer *fb,
    - int x, int y, int atomic)
    +static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
    + struct drm_framebuffer *fb,
    + int x, int y, int atomic)
    {
    struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
    struct drm_device *dev = crtc->dev;
    @@ -1093,12 +1093,6 @@ static int evergreen_crtc_do_set_base(st
    WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
    (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);

    - if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
    - WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
    - EVERGREEN_INTERLEAVE_EN);
    - else
    - WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
    -
    if (!atomic && fb && fb != crtc->fb) {
    radeon_fb = to_radeon_framebuffer(fb);
    rbo = radeon_fb->obj->driver_private;
    @@ -1247,12 +1241,6 @@ static int avivo_crtc_do_set_base(struct
    WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
    (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);

    - if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
    - WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
    - AVIVO_D1MODE_INTERLEAVE_EN);
    - else
    - WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
    -
    if (!atomic && fb && fb != crtc->fb) {
    radeon_fb = to_radeon_framebuffer(fb);
    rbo = radeon_fb->obj->driver_private;
    @@ -1276,7 +1264,7 @@ int atombios_crtc_set_base(struct drm_cr
    struct radeon_device *rdev = dev->dev_private;

    if (ASIC_IS_DCE4(rdev))
    - return evergreen_crtc_do_set_base(crtc, old_fb, x, y, 0);
    + return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
    else if (ASIC_IS_AVIVO(rdev))
    return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
    else
    @@ -1291,7 +1279,7 @@ int atombios_crtc_set_base_atomic(struct
    struct radeon_device *rdev = dev->dev_private;

    if (ASIC_IS_DCE4(rdev))
    - return evergreen_crtc_do_set_base(crtc, fb, x, y, 1);
    + return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
    else if (ASIC_IS_AVIVO(rdev))
    return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
    else
    --- a/drivers/gpu/drm/radeon/radeon_encoders.c
    +++ b/drivers/gpu/drm/radeon/radeon_encoders.c
    @@ -1465,11 +1465,21 @@ atombios_apply_encoder_quirks(struct drm
    }

    /* set scaler clears this on some chips */
    - /* XXX check DCE4 */
    - if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
    - if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
    - WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
    - AVIVO_D1MODE_INTERLEAVE_EN);
    + if (ASIC_IS_AVIVO(rdev) &&
    + (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
    + if (ASIC_IS_DCE4(rdev)) {
    + if (mode->flags & DRM_MODE_FLAG_INTERLACE)
    + WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
    + EVERGREEN_INTERLEAVE_EN);
    + else
    + WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
    + } else {
    + if (mode->flags & DRM_MODE_FLAG_INTERLACE)
    + WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
    + AVIVO_D1MODE_INTERLEAVE_EN);
    + else
    + WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
    + }
    }
    }




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