[lkml]   [2011]   [Feb]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
    SubjectRe: [PATCH 0/2] jump label: 2.6.38 updates
    On 02/15/2011 03:01 AM, Will Newton wrote:
    > The CPU in question has two sets of instructions:
    > load/store - these go via the cache (write through)
    > ll/sc - these operate literally as if there is no cache (they do not
    > hit on read or write)
    > This may or may not be a sensible way to architect a CPU, but I think
    > it is possible to make it work. Making it work efficiently is more of
    > a challenge.

    a) What "CPU in question" is this?
    b) Why should we let this particular insane CPU slow ALL OTHER CPUs down?


    H. Peter Anvin, Intel Open Source Technology Center
    I work for Intel. I don't speak on their behalf.

     \ /
      Last update: 2011-02-15 14:35    [W:0.017 / U:52.152 seconds]
    ©2003-2017 Jasper Spaans. hosted at Digital OceanAdvertise on this site