Messages in this thread |  | | | Date | Mon, 14 Feb 2011 22:37:55 +0000 | | From | Matt Fleming <> | | Subject | Re: [PATCH 0/2] jump label: 2.6.38 updates |
| |
On Mon, 14 Feb 2011 13:46:00 -0800 (PST) David Miller <davem@davemloft.net> wrote:
> From: Steven Rostedt <rostedt@goodmis.org> > Date: Mon, 14 Feb 2011 16:39:36 -0500 > > > Thus it is not about global, as global is updated by normal means > > and will update the caches. atomic_t is updated via the ll/sc that > > ignores the cache and causes all this to break down. IOW... broken > > hardware ;) > > I don't see how cache coherency can possibly work if the hardware > behaves this way.
Cache coherency is still maintained provided writes/reads both go through the cache ;-)
The problem is that for read-modify-write operations the arbitration logic that decides who "wins" and is allowed to actually perform the write, assuming two or more CPUs are competing for a single memory address, is not implemented in the cache controller, I think. I'm not a hardware engineer and I never understood how the arbitration logic worked but I'm guessing that's the reason that the ll/sc instructions bypass the cache.
Which is why the atomic_t functions worked out really well for that arch, such that any accesses to an atomic_t * had to go through the wrapper functions.
|  |