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    Subject[tip:x86/urgent] x86/mtrr: Resolve inconsistency with Intel processor manual
    Commit-ID:  8dbf4a30033ff61091015f0076e872b5c8f717cc
    Gitweb: http://git.kernel.org/tip/8dbf4a30033ff61091015f0076e872b5c8f717cc
    Author: Ajaykumar Hotchandani <ajaykumar.hotchandani@oracle.com>
    AuthorDate: Fri, 11 Nov 2011 18:31:57 +0530
    Committer: Ingo Molnar <mingo@elte.hu>
    CommitDate: Mon, 5 Dec 2011 15:06:15 +0100

    x86/mtrr: Resolve inconsistency with Intel processor manual

    Following is from Notes of section 11.5.3 of Intel processor
    manual available at:

    http://www.intel.com/Assets/PDF/manual/325384.pdf

    For the Pentium 4 and Intel Xeon processors, after the sequence of
    steps given above has been executed, the cache lines containing the
    code between the end of the WBINVD instruction and before the
    MTRRS have actually been disabled may be retained in the cache
    hierarchy. Here, to remove code from the cache completely, a
    second WBINVD instruction must be executed after the MTRRs have
    been disabled.

    This patch provides resolution for that.

    Ideally, I will like to make changes only for Pentium 4 and Xeon
    processors. But, I am not finding easier way to do it.
    And, extra wbinvd() instruction does not hurt much for other
    processors.

    Signed-off-by: Ajaykumar Hotchandani <ajaykumar.hotchandani@oracle.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Arjan van de Ven <arjan@linux.intel.com>
    Cc: Lucas De Marchi <lucas.demarchi@profusion.mobi>
    Link: http://lkml.kernel.org/r/4EBD1CC5.3030008@oracle.com
    Signed-off-by: Ingo Molnar <mingo@elte.hu>
    ---
    arch/x86/kernel/cpu/mtrr/generic.c | 1 +
    1 files changed, 1 insertions(+), 0 deletions(-)

    diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
    index e1fe7f4..97b2635 100644
    --- a/arch/x86/kernel/cpu/mtrr/generic.c
    +++ b/arch/x86/kernel/cpu/mtrr/generic.c
    @@ -694,6 +694,7 @@ static void prepare_set(void) __acquires(set_atomicity_lock)

    /* Disable MTRRs, and set the default type to uncached */
    mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
    + wbinvd();
    }

    static void post_set(void) __releases(set_atomicity_lock)

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