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SubjectRE: [PATCH 1/1] r8169.c correct MSIEnable register offset
Date


> -----Original Message-----
> From: David Miller [mailto:davem@davemloft.net]
> Sent: Thursday, December 15, 2011 2:44 PM
> To: romieu@fr.zoreil.com
> Cc: cantona@cantona.no-ip.org; Hayeswang;
> linux-kernel@vger.kernel.org; nic_swsd; netdev@vger.kernel.org
> Subject: Re: [PATCH 1/1] r8169.c correct MSIEnable register offset
>
> From: Francois Romieu <romieu@fr.zoreil.com>
> Date: Wed, 14 Dec 2011 22:37:13 +0100
>
> > Su Kang Yin <cantona@cantona.no-ip.org> :
> >> correct MSIEnable (bit 5) register to Config1 (offset
> 0x52) instead of
> >> Config2 (offset 0x53)
> >

The bit 5 of config1 (0x52) is reserved. And the bit 5 of Config2 (0x53) is
MSIEnable only for 8169 controler series.

> > I wonder where the inspiration for the MSIEnable bit came from.
> > It looks like something was confused with the Message Control word
> > in PCI space.
> >
> > Imho you can simply remove it altogether.
>
> Someone should find out what the real situation is with this.
>
> Maybe it mirrors the PCI config space setting and is read-only, maybe
> not. But it should be determined for sure before changing this. :-)
>



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