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Subject[PATCH 4/6] x86, mce: Add mechanism to safely save information in MCE handler
Machine checks on Intel cpus interrupt execution on all cpus, regardless
of interrupt masking. We have a need to save some data about the cause
of the machine check (physical address) in the machine check handler that
can be retrieved later to attempt recovery in a more flexible execution
state.

Signed-off-by: Tony Luck <tony.luck@intel.com>
---
arch/x86/kernel/cpu/mcheck/mce.c | 51 ++++++++++++++++++++++++++++++++++++++
1 files changed, 51 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 43f22c8..9b83b7d 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -887,6 +887,57 @@ static void mce_clear_state(unsigned long *toclear)
}

/*
+ * Need to save faulting physical address associated with a process
+ * in the machine check handler some place where we can grab it back
+ * later in mce_notify_process()
+ */
+#define MAX_MCE_INFO 16
+struct mce_info {
+ atomic_t inuse;
+ struct task_struct *t;
+ __u64 paddr;
+} mce_info[MAX_MCE_INFO];
+
+static void mce_save_info(__u64 addr)
+{
+ int i;
+
+ for (i = 0; i < MAX_MCE_INFO; i++)
+ if (atomic_cmpxchg(&mce_info[i].inuse, 0, 1) == 0) {
+ mce_info[i].t = current;
+ mce_info[i].paddr = addr;
+ return;
+ }
+
+ mce_panic("Too many concurrent recoverable errors", NULL, NULL);
+}
+
+static int mce_find_info(__u64 *paddr)
+{
+ int i;
+
+ for (i = 0; i < MAX_MCE_INFO; i++)
+ if (atomic_read(&mce_info[i].inuse) &&
+ mce_info[i].t == current) {
+ *paddr = mce_info[i].paddr;
+ return 1;
+ }
+ return 0;
+}
+
+static void mce_clear_info(void)
+{
+ int i;
+
+ for (i = 0; i < MAX_MCE_INFO; i++)
+ if (atomic_read(&mce_info[i].inuse) &&
+ mce_info[i].t == current) {
+ atomic_set(&mce_info[i].inuse, 0);
+ return;
+ }
+}
+
+/*
* The actual machine check handler. This only handles real
* exceptions when something got corrupted coming in through int 18.
*
--
1.7.3.1


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