Messages in this thread |  | | | Date | Tue, 22 Nov 2011 10:27:25 -0700 | | From | Matthew Wilcox <> | | Subject | Re: extra large DMA buffer for PCI-E device under UIO |
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On Tue, Nov 22, 2011 at 11:54:22AM -0500, Jean-Francois Dagenais wrote: > That is quite interesting. It really seems like my VT-d recipe to create 128MB for my PCI-e > FPGA to write into is covered by this patch. > > My problem is that our FPGA is connected to one of the atom E6XX's PCI-e links, so no > iommu :( Since our first product had VT-d, the FPGA, uio based module and userspace > code is designed such that the device sees a huge contiguous memory chunk. This is key > to the performance of the FPGA, which is essentially decoupled from the CPU for it's real-time > acquisition.
Is it really key? If you supported, ohidon'tknow, 2MB pages, you'd need 64 entries in the FPGA to store the addresses of those 2MB pages, which doesn't sound like a huge burden.
-- Matthew Wilcox Intel Open Source Technology Centre "Bill, look, we understand that you're interested in selling us this operating system, but compare it to ours. We can't possibly take such a retrograde step."
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