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    Subject[PATCH 7/9] x86, RAS: Add function enabling direct writes to MCE MSRs
    Date
    From: Borislav Petkov <borislav.petkov@amd.com>

    Normally, writing to MCE MSRs causes a #GP. Add a function to enable
    direct accesses to those MSRs.

    Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
    ---
    arch/x86/kernel/cpu/ras/amd/mce-inject.c | 24 ++++++++++++++++++++++++
    1 files changed, 24 insertions(+), 0 deletions(-)

    diff --git a/arch/x86/kernel/cpu/ras/amd/mce-inject.c b/arch/x86/kernel/cpu/ras/amd/mce-inject.c
    index fdec361..1b797bd 100644
    --- a/arch/x86/kernel/cpu/ras/amd/mce-inject.c
    +++ b/arch/x86/kernel/cpu/ras/amd/mce-inject.c
    @@ -53,6 +53,30 @@ DEFINE_SIMPLE_ATTRIBUTE(misc_fops, inj_misc_get, inj_misc_set, "%llx\n");
    DEFINE_SIMPLE_ATTRIBUTE(addr_fops, inj_addr_get, inj_addr_set, "%llx\n");

    /*
    + * Caller needs to be make sure this cpu doesn't disappear
    + * from under us, i.e.: get_cpu/put_cpu.
    + */
    +static int toggle_hw_mce_inject(unsigned int cpu, bool enable)
    +{
    + u32 l, h;
    + int err;
    +
    + err = rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h);
    + if (err) {
    + printk(KERN_ERR "%s: error reading HWCR\n", __func__);
    + return err;
    + }
    +
    + enable ? (l |= BIT(18)) : (l &= ~BIT(18));
    +
    + err = wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h);
    + if (err)
    + printk(KERN_ERR "%s: error writing HWCR\n", __func__);
    +
    + return err;
    +}
    +
    +/*
    * This denotes into which bank we're injecting and triggers
    * the injection, at the same time.
    */
    --
    1.7.4.rc2


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