Messages in this thread | | | Date | Tue, 11 Oct 2011 11:40:21 +0800 | Subject | Re: [Question] PM-QoS: PM_QOS_CPU_DMA_LATENCY == interrupt latency? | From | Ming Lei <> |
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Hi,
On Tue, Oct 11, 2011 at 10:26 AM, Shaohua Li <shli@kernel.org> wrote: > 2011/10/11 Ming Lei <tom.leiming@gmail.com>: >> Hi, >> >> On Tue, Oct 11, 2011 at 9:49 AM, Shaohua Li <shli@kernel.org> wrote: >> >>> As Alan explained, PM_QOS_CPU_DMA_LATENCY is for dma snooping. For example, >>> in x86, cpu snoop dma. when cpu is in idle state, cpu need snoop >>> device dma activity, there >>> is latency involved for idle state. >>> >> >> I see, thanks for your clarification. >> >> I also have two further questions about it: >> >> - Except for dma snooping purpose, are there any other cases in which >> PM_QOS_CPU_DMA_LATENCY is required? > it's the main motivation, IIRC, don't know other platforms
If so, maybe all device drivers which support DMA transfer should have used PM_QOS_CPU_DMA_LATENCY, but why only few drivers did it?
> >> - Are all CPUs required to be involved to dma snoop? Or only one CPU >> is enough? If one is enough, maybe we can allow other CPUs to reach >> deeper idle state. > then how can you make cache coherency between the cpus? >
Seems ARM supports cache maintenance operations from software[1], but I don't know how to do it on x86, :-)
[1], http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0228a/index.html
thanks, -- Ming Lei
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