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    Subject[PATCH RESEND 5/6] MIPS: Install handlers for BMIPS software IRQs
    Date
    BMIPS4350/4380/5000 CMT/SMT all use SW INT0/INT1 for inter-thread
    signaling.

    Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
    ---
    arch/mips/kernel/irq_cpu.c | 14 ++++++--------
    1 files changed, 6 insertions(+), 8 deletions(-)

    diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
    index 0262abe..70d4736 100644
    --- a/arch/mips/kernel/irq_cpu.c
    +++ b/arch/mips/kernel/irq_cpu.c
    @@ -107,14 +107,12 @@ void __init mips_cpu_irq_init(void)
    clear_c0_status(ST0_IM);
    clear_c0_cause(CAUSEF_IP);

    - /*
    - * Only MT is using the software interrupts currently, so we just
    - * leave them uninitialized for other processors.
    - */
    - if (cpu_has_mipsmt)
    - for (i = irq_base; i < irq_base + 2; i++)
    - set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
    - handle_percpu_irq);
    + /* Software interrupts are used for MT/CMT IPI */
    + for (i = irq_base; i < irq_base + 2; i++)
    + set_irq_chip_and_handler(i, cpu_has_mipsmt ?
    + &mips_mt_cpu_irq_controller :
    + &mips_cpu_irq_controller,
    + handle_percpu_irq);

    for (i = irq_base + 2; i < irq_base + 8; i++)
    set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
    --
    1.7.0.4


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