Messages in this thread |  | | | Date | Thu, 27 Jan 2011 13:47:56 +0100 | | From | Ingo Molnar <> | | Subject | Re: [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs |
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* Hans Rosenfeld <hans.rosenfeld@amd.com> wrote:
> On Wed, Jan 26, 2011 at 03:56:08PM -0500, Ingo Molnar wrote: > > * Hans Rosenfeld <hans.rosenfeld@amd.com> wrote: > > > +#ifdef CONFIG_SMP > > > +int amd_get_subcaches(int cpu) > > > > Well, sprinkling it with CONFIG_SMP is pretty ugly. Also, there's no fundamental > > reason why this shouldnt work with UP. Yes, it makes most sense on SMP but such code > > should be SMP-invariant. > > True, it is pretty ugly. And while the feature is pretty useless for UP, > it would still work for compute_unit_id 0 in that case. > > The problem is that cpuinfo_x86.compute_unit_id etc. don't exist unless > CONFIG_SMP is enabled. I don't think there is any reason why this should > be that way, but changing this just for this particular L3 feature seems > too intrusive. Do you really want me to do that?
All the CONFIG_X86_HT #ifdefs in arch/x86/kernel/cpu/amd.c look pretty ugly too - and it's not really a properly modularized solution.
We generally want to unify the SMP and UP kernels as much as possible. 'CONFIG_SMP' is not really a property of the hardware, it's a property of the software.
If some topology information should be excluded then it can already be done by turning off CONFIG_CPU_SUP_AMD under CONFIG_EXPERT.
Thanks,
Ingo
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