Messages in this thread Patch in this message | | | Date | Wed, 26 Jan 2011 10:58:19 GMT | From | tip-bot for Hans Rosenfeld <> | Subject | [tip:x86/amd-nb] x86, amd: Enable L3 cache index disable on family 0x15 |
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Commit-ID: b453de02b786c63b8928ec822401468131db0a9b Gitweb: http://git.kernel.org/tip/b453de02b786c63b8928ec822401468131db0a9b Author: Hans Rosenfeld <hans.rosenfeld@amd.com> AuthorDate: Mon, 24 Jan 2011 16:05:41 +0100 Committer: Ingo Molnar <mingo@elte.hu> CommitDate: Wed, 26 Jan 2011 08:28:23 +0100
x86, amd: Enable L3 cache index disable on family 0x15
AMD family 0x15 CPUs support L3 cache index disable, so enable it on them.
Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> Cc: <andreas.herrmann3@amd.com> LKML-Reference: <1295881543-572552-3-git-send-email-hans.rosenfeld@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> --- arch/x86/kernel/amd_nb.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 0a99f71..a4f394c 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -85,6 +85,9 @@ int amd_cache_northbridges(void) boot_cpu_data.x86_mask >= 0x1)) amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; + if (boot_cpu_data.x86 == 0x15) + amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; + return 0; } EXPORT_SYMBOL_GPL(amd_cache_northbridges);
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