Messages in this thread | | | Date | Thu, 13 Jan 2011 18:14:19 +0100 | Subject | Re: [RFC PATCH 2/3 v3] perf: Implement Nehalem uncore pmu | From | Stephane Eranian <> |
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Lin,
On Thu, Dec 2, 2010 at 6:20 AM, Lin Ming <ming.m.lin@intel.com> wrote: > +static void uncore_pmu_enable_all(int nmi_core) > +{ > + u64 ctrl; > + > + ctrl = ((1 << UNCORE_NUM_GENERAL_COUNTERS) - 1) | MSR_UNCORE_PERF_GLOBAL_CTRL_EN_FC0; > + > + /* Route all interrupts to the first core that accesses uncore */ > + ctrl |= 1ULL << (48 + nmi_core); > + > + wrmsrl(MSR_UNCORE_PERF_GLOBAL_CTRL, ctrl); > +}
Are you sure nmi_core is always between 0-3 on a 4-core system and 0-5 on a 6-core system? In other words, is that what topology_core_id(raw_smp_processor_id()) returns?
Note that, unfortunately, I have not seen documentation that says on 6-core system UNC_GLOBAL_CTRL has 6 interrupt target bits, but it would make sense.
Otherwise, you will get a kernel panic when you wrmsr UNC_GLOBAL_CTRL.
> + > + if (uncore->n_events == 1) { > + nmi_core = topology_core_id(raw_smp_processor_id()); > + uncore->nmi_core = nmi_core; > + uncore_pmu_enable_all(nmi_core); > + } -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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