Messages in this thread | | | Date | Wed, 29 Sep 2010 18:00:35 +0200 | Subject | Re: [tip:perf/urgent] perf, x86: Catch spurious interrupts after disabling counters | From | Stephane Eranian <> |
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On Wed, Sep 29, 2010 at 5:45 PM, Cyrill Gorcunov <gorcunov@gmail.com> wrote: > On Wed, Sep 29, 2010 at 05:33:07PM +0200, Stephane Eranian wrote: >> Robert, >> >> There is something else bothering me with cpuc->running. >> >> It is not reset outside of the interrupt handler. So what if >> event scheduling shuffles things around and an event is >> moved somewhere else. Don't you need to clear the >> cpuc->running[idx] for the old counter index? >> >> > > Both bitmasks are set and test with same index though it might > be a bit obscure scheme (we could be clearing this bit in > x86_pmu_stop but it just a wasting cycles). > But you cannot clear it in x86_pmu_stop() because otherwise it turns into active_mask[]. My understanding is that you need to remember this counter has been active at some point in the past.
My point is that you cannot keep this around forever. After a "while" it becomes stale and you have to remove it otherwise you may wrongly increment handled.
Here is a scenario:
event A -> counter 0, cpuc->running = 0x1 active_mask = 0x1 move A event A -> counter 1, cpuc->running = 0x3, active_mask = 0x2
No interrupt, we are just counting for a short period. Then, you get an NMI interrupt, suppose it is not generated by the PMU, it is destined for another handler.
For i=0, you have (active_mask & 0x1) == 0, but (running & 0x1) == 1, you mark the interrupt as handled, i.e., you swallow it, the actual handler never gets it.
> Btw, since x86 architectural and p4 are using same tests for > running I presume better to have some helper rather then > open coded pile? > > Cyrill >
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