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SubjectRe: [tip:perf/urgent] perf, x86: Catch spurious interrupts after disabling counters
On Wed, Sep 29, 2010 at 05:12:53PM +0200, Robert Richter wrote:
> On 29.09.10 17:01:40, Robert Richter wrote:
> > Right, I wasn't remembering correctly, it was P6 and core. And yes, P4
> > requires the fix. Will send a patch for this.
>
> Ok, Cyrill is sending the patch.
>
> Thanks,
>
> -Robert
>

Managed to implement it earlier then I thought.

Cyrill
---
Subject: [PATCH -tip] perf, x86: Handle in flight IRQs on P4 platform
Stephane reported we've missed to guard P4 platform
against spurious in-flight performance IRQs. Fix it.

[ the patch is a complement to commit 63e6be6d98e1 ]

Reported-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
CC: Robert Richter <robert.richter@amd.com>
CC: Lin Ming <ming.m.lin@intel.com>
---
arch/x86/kernel/cpu/perf_event_p4.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
Index: linux-2.6.git/arch/x86/kernel/cpu/perf_event_p4.c
=====================================================================
--- linux-2.6.git.orig/arch/x86/kernel/cpu/perf_event_p4.c
+++ linux-2.6.git/arch/x86/kernel/cpu/perf_event_p4.c
@@ -904,8 +904,12 @@ static int p4_pmu_handle_irq(struct pt_r
for (idx = 0; idx < x86_pmu.num_counters; idx++) {
int overflow;

- if (!test_bit(idx, cpuc->active_mask))
+ if (!test_bit(idx, cpuc->active_mask)) {
+ /* catch in-flight IRQs */
+ if (__test_and_clear_bit(idx, cpuc->running))
+ handled++;
continue;
+ }

event = cpuc->events[idx];
hwc = &event->hw;

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