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    SubjectRe: [tip:perf/urgent] perf, x86: Catch spurious interrupts after disabling counters

    On 29.09.10 08:26:41, Stephane Eranian wrote:
    > You've applied the fix only to the generic X86 interrupt handler
    > which is currently used by AMD64 processors.

    (... and P4).

    > It seems to me that this "in-flight interrupt after disable" problem
    > may also happen on Intel and should therefore also be added
    > to intel_pmu_handle_irq(). Don't you think so?

    It only happens if the active_mask is used for checking single
    counters for overflows.

    Systems with Intel Architectural Perfmon use the status mask msr to
    determine which counter overflowed. In intel_pmu_handle_irq() the
    handled counter is incremented in this case even if the counter is not
    active, so everything should be fine here.


    Advanced Micro Devices, Inc.
    Operating System Research Center

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