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SubjectRe: [PATCH] perf, x86: catch spurious interrupts after disabling counters
On 15.09.10 12:36:27, Stephane Eranian wrote:
> On Wed, Sep 15, 2010 at 6:20 PM, Robert Richter <robert.richter@amd.com> wrote:
> > On 14.09.10 19:41:32, Robert Richter wrote:
> >> I found the reason why we get the unknown nmi. For some reason
> >> cpuc->active_mask in x86_pmu_handle_irq() is zero. Thus, no counters
> >> are handled when we get an nmi. It seems there is somewhere a race
> >> accessing the active_mask. So far I don't have a fix available.
> >> Changing x86_pmu_stop() did not help:
> >
> > The patch below for tip/perf/urgent fixes this.
> >
> > -Robert
> >
> > From 4206a086f5b37efc1b4d94f1d90b55802b299ca0 Mon Sep 17 00:00:00 2001
> > From: Robert Richter <robert.richter@amd.com>
> > Date: Wed, 15 Sep 2010 16:12:59 +0200
> > Subject: [PATCH] perf, x86: catch spurious interrupts after disabling counters
> >
> > Some cpus still deliver spurious interrupts after disabling a counter.
>
> Most likely the interrupt was in flight at the time you disabled it.

I tried to clear the bit in the active_mask after disabling the
counter (writing to the msr), which did not solve it. Shouldn't the
counter be disabled immediatly? Maybe clearing the INT bit would have
been worked too, but I was not sure about side effects.

> Does the counter value reflect this?

Yes, the disabled bit was cleared after reading the evntsel msr and
the ctr value have had about 400 cycles (it could have been
overflowed, though we actually can't say since the counter was
disabled).

> Were you also getting this if you were only measuring at the user level?

I tried only

perf record ./hackbench 10

which triggered it on my system.

-Robert

--
Advanced Micro Devices, Inc.
Operating System Research Center



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