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SubjectRe: [PATCH] perf, x86: catch spurious interrupts after disabling counters
On Wed, Sep 15, 2010 at 06:20:34PM +0200, Robert Richter wrote:
> On 14.09.10 19:41:32, Robert Richter wrote:
> > I found the reason why we get the unknown nmi. For some reason
> > cpuc->active_mask in x86_pmu_handle_irq() is zero. Thus, no counters
> > are handled when we get an nmi. It seems there is somewhere a race
> > accessing the active_mask. So far I don't have a fix available.
> > Changing x86_pmu_stop() did not help:
>
> The patch below for tip/perf/urgent fixes this.
>
> -Robert
>
> From 4206a086f5b37efc1b4d94f1d90b55802b299ca0 Mon Sep 17 00:00:00 2001
> From: Robert Richter <robert.richter@amd.com>
> Date: Wed, 15 Sep 2010 16:12:59 +0200
> Subject: [PATCH] perf, x86: catch spurious interrupts after disabling counters
>
> Some cpus still deliver spurious interrupts after disabling a counter.
> This caused 'undelivered NMI' messages. This patch fixes this.
>
> Signed-off-by: Robert Richter <robert.richter@amd.com>
> ---
...

Hi Robert, thanks a lot for tracking this issue! I might be missing
something but why don't you clean this ->running mask bits on pmu-stop?
What if counter gets disabled/freed or whatever before issue any nmis?
Another question I have still -- is this an hardware issue in general?

-- Cyrill


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