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    Subject[21/59] drm/i915/edp: Flush the write before waiting for PLLs
    2.6.32-stable review patch.  If anyone has any objections, please let us know.

    ------------------

    From: Chris Wilson <chris@chris-wilson.co.uk>

    commit 5ddb954b9ee50824977d2931e0ff58b3050b337d upstream.

    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
    Signed-off-by: Eric Anholt <eric@anholt.net>
    Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

    ---
    drivers/gpu/drm/i915/intel_display.c | 1 +
    1 file changed, 1 insertion(+)

    --- a/drivers/gpu/drm/i915/intel_display.c
    +++ b/drivers/gpu/drm/i915/intel_display.c
    @@ -1402,6 +1402,7 @@ static void igdng_enable_pll_edp (struct
    dpa_ctl = I915_READ(DP_A);
    dpa_ctl |= DP_PLL_ENABLE;
    I915_WRITE(DP_A, dpa_ctl);
    + POSTING_READ(DP_A);
    udelay(200);
    }




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