Messages in this thread Patch in this message | | | Date | Tue, 24 Aug 2010 15:44:29 -0700 | From | Greg KH <> | Subject | [024/114] perf, x86: P4 PMU -- update nmi irq statistics and unmask lvt entry properly |
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2.6.35-stable review patch. If anyone has any objections, please let us know.
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From: Cyrill Gorcunov <gorcunov@openvz.org>
commit 1c250d709fdc8aa5bf42d90be99428a01a256a55 upstream.
In case if last active performance counter is not overflowed at moment of NMI being triggered by another counter, the irq statistics may miss an update stage. As a more serious consequence -- apic quirk may not be triggered so apic lvt entry stay masked.
Tested-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Stephane Eranian <eranian@google.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Frederic Weisbecker <fweisbec@gmail.com> LKML-Reference: <20100805150917.GA6311@lenovo> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
--- arch/x86/kernel/cpu/perf_event_p4.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)
--- a/arch/x86/kernel/cpu/perf_event_p4.c +++ b/arch/x86/kernel/cpu/perf_event_p4.c @@ -581,6 +581,7 @@ static int p4_pmu_handle_irq(struct pt_r cpuc = &__get_cpu_var(cpu_hw_events); for (idx = 0; idx < x86_pmu.num_counters; idx++) { + int overflow; if (!test_bit(idx, cpuc->active_mask)) continue; @@ -591,12 +592,14 @@ static int p4_pmu_handle_irq(struct pt_r WARN_ON_ONCE(hwc->idx != idx); /* it might be unflagged overflow */ - handled = p4_pmu_clear_cccr_ovf(hwc); + overflow = p4_pmu_clear_cccr_ovf(hwc); val = x86_perf_event_update(event); - if (!handled && (val & (1ULL << (x86_pmu.cntval_bits - 1)))) + if (!overflow && (val & (1ULL << (x86_pmu.cntval_bits - 1)))) continue; + handled += overflow; + /* event overflow for sure */ data.period = event->hw.last_period; @@ -612,7 +615,7 @@ static int p4_pmu_handle_irq(struct pt_r inc_irq_stat(apic_perf_irqs); } - return handled; + return handled > 0; } /*
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