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    SubjectRe: [PATCH] [MTD] [NAND] pxa3xx: fix ns2cycle equation
    On Mon, Aug 16, 2010 at 6:32 PM, David Woodhouse <> wrote:
    > On Mon, 2010-08-16 at 16:09 +0800, Axel Lin wrote:
    >> Test on a PXA310 platform with Samsung K9F2G08X0B NAND flash,
    >> with tCH=5 and clk is 156MHz, ns2cycle(5, 156000000) returns -1.
    >> ns2cycle returns negtive value will break NDTR0_tXX macros.
    >> After checking the commit log, I found the problem is introduced by
    >> commit 5b0d4d7c8a67c5ba3d35e6ceb0c5530cc6846db7
    >> "[MTD] [NAND] pxa3xx: convert from ns to clock ticks more accurately"
    >> To get num of clock cycles, we use below equation:
    >> num of clock cycles = time (ns) / one clock cycle (ns) + 1
    >> We need to add 1 cycle here because integer division will truncate the result.
    >> It is possible the developers set the Min values in SPEC for timing settings.
    >> Thus the truncate may cause problem, and it is safe to add an extra cycle here.
    >> The various fields in NDTR{01} are in units of clock ticks minus one,
    >> thus we should subtract 1 cycle then.
    >> Thus the correct equation should be:
    >> num of clock cycles = time (ns) / one clock cycle (ns) + 1 - 1
    >>                     = time (ns) / one clock cycle (ns)
    > Looks sane to me; thanks. Wants to go to stable@ too, yes?
    > Can I have an Acked-By: from Matt and/or Eric?

    Acked-by: Eric Miao <>
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