Messages in this thread | | | Date | Thu, 15 Jul 2010 23:56:40 +0200 | From | "H. Peter Anvin" <> | Subject | Re: [PATCH 1/2] x86: fix keeping track of AMD C1E |
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On 07/16/2010 08:39 AM, Borislav Petkov wrote: > From: "H. Peter Anvin"<hpa@zytor.com> > Date: Fri, Jul 16, 2010 at 12:25:39AM -0400 > >> On 07/14/2010 02:31 PM, Michal Schmidt wrote: >>> >>> This suggests that another way to fix my problem would be this (tested): >>> >> >> This is a change of semantics from an AND to an OR across CPUs... > > You mean the c1e_detected variable and the CPUID flag, right? Well, > frankly and if I'm not missing anything, we actually only need to track > when either bits [27,28] get set in that MSR - MSR_K8_INT_PENDING_MSG - > in order to do timer broadcast. > > And strictly speaking, we don't need a variable for that at all (nor a > synthetic CPUID flag, for that matter) - we can simply read the MSR as > much as we'd like after we've detected that this CPU supports C1E. > > But having the value cached is faster and doesn't enlarge checking > code in acpi_processor_cstate_check(). > > I think the reason for adding the syntetic cpuid flag is only to > communicate to the ACPI processor module that we don't support deeper > C-states on a C1E machine, see a8d6829044901a67732904be5f1eacdf8539604f. > So we don't strictly need it and we can only export c1e_detected to the > rest for simplicity. >
No, the difference between using a separate variable and the CPU feature bit is that CPU feature bit is ANDed across all CPUs, whereas this variable is set if it is set on *any* CPU.
-hpa
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