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Subject[PATCH] x86/sfi: fix ioapic gsi range
Date
SFI based platforms should have zero based gsi_base for IOAPICs found in SFI
tables. The current code sets gsi_base starting from 1 when registering ioapic.
The result is that Moorestown platform would have wrong mp_gsi_routing for each
ioapic.

Background:
In Moorestown/Medfield platforms, there is no legacy IRQs, all gsis and irqs
are one to one mapped, including those < 16. Specifically, IRQ0 and IRQ1 are
used for per-cpu timers. So without this patch, IOAPIC pin to IRQ mapping is
off by one.

Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
---
arch/x86/kernel/sfi.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/x86/kernel/sfi.c b/arch/x86/kernel/sfi.c
index 7ded578..8d31950 100644
--- a/arch/x86/kernel/sfi.c
+++ b/arch/x86/kernel/sfi.c
@@ -87,14 +87,17 @@ static int __init sfi_parse_ioapic(struct sfi_table_header *table)
struct sfi_table_simple *sb;
struct sfi_apic_table_entry *pentry;
int i, num;
+ u32 gsi_base;

sb = (struct sfi_table_simple *)table;
num = SFI_GET_NUM_ENTRIES(sb, struct sfi_apic_table_entry);
pentry = (struct sfi_apic_table_entry *)sb->pentry;

+ gsi_base = gsi_end;
for (i = 0; i < num; i++) {
- mp_register_ioapic(i, pentry->phys_addr, gsi_end + 1);
+ mp_register_ioapic(i, pentry->phys_addr, gsi_base);
pentry++;
+ gsi_base = gsi_end + 1;
}

WARN(pic_mode, KERN_WARNING
--
1.6.3.3


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