Messages in this thread Patch in this message | | | Date | Wed, 30 Jun 2010 17:45:19 -0700 | From | "Darrick J. Wong" <> | Subject | [PATCH] x86, Calgary: Increase max PHB number |
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The x3950 family can have as many as 256 PCI buses in a single system, so change the limits to the maximum. Since there can only be 256 PCI buses in one domain, we no longer need the BUG_ON check.
Signed-off-by: Darrick J. Wong <djwong@us.ibm.com> ---
arch/x86/kernel/pci-calgary_64.c | 4 +--- 1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c index 0b96b55..078d4ec 100644 --- a/arch/x86/kernel/pci-calgary_64.c +++ b/arch/x86/kernel/pci-calgary_64.c @@ -110,7 +110,7 @@ int use_calgary __read_mostly = 0; * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256 * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128 */ -#define MAX_PHB_BUS_NUM 384 +#define MAX_PHB_BUS_NUM 256 #define PHBS_PER_CALGARY 4 @@ -1056,8 +1056,6 @@ static int __init calgary_init_one(struct pci_dev *dev) struct iommu_table *tbl; int ret; - BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM); - bbar = busno_to_bbar(dev->bus->number); ret = calgary_setup_tar(dev, bbar); if (ret)
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