lkml.org 
[lkml]   [2010]   [Jun]   [29]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH -next] tile: remove homegrown L1_CACHE_ALIGN macro
This looks fine, thanks.

Acked-by: Chris Metcalf <cmetcalf@tilera.com>

On 6/29/2010 3:32 AM, FUJITA Tomonori wrote:
> Let's use the standard L1_CACHE_ALIGN macro instead.
>
> Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
> ---
> arch/tile/include/asm/cache.h | 1 -
> 1 files changed, 0 insertions(+), 1 deletions(-)
>
> diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h
> index c2b7dcf..ee59714 100644
> --- a/arch/tile/include/asm/cache.h
> +++ b/arch/tile/include/asm/cache.h
> @@ -20,7 +20,6 @@
> /* bytes per L1 data cache line */
> #define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE()
> #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
> -#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1)) & -L1_CACHE_BYTES)
>
> /* bytes per L1 instruction cache line */
> #define L1I_CACHE_SHIFT CHIP_L1I_LOG_LINE_SIZE()
>

--
Chris Metcalf, Tilera Corp.
http://www.tilera.com



\
 
 \ /
  Last update: 2010-06-29 15:13    [W:0.036 / U:1.224 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site