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    Subject[PATCH 01/11] perf, x86: Fix Nehalem PMU quirk
    The idea was to run all three counters, which means we need to
    program 7 into the enable mask, not 3 (which is two bits).

    Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
    ---
    Index: linux-2.6/arch/x86/kernel/cpu/perf_event_intel.c
    ===================================================================
    --- linux-2.6.orig/arch/x86/kernel/cpu/perf_event_intel.c
    +++ linux-2.6/arch/x86/kernel/cpu/perf_event_intel.c
    @@ -504,7 +504,7 @@ static void intel_pmu_nhm_enable_all(int
    wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + 1, 0x4300B1);
    wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + 2, 0x4300B5);

    - wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x3);
    + wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x7);
    wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);

    for (i = 0; i < 3; i++) {



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