Messages in this thread Patch in this message | | | Date | Thu, 3 Jun 2010 01:23:04 +0400 | From | Cyrill Gorcunov <> | Subject | [PATCH -tip] perf, x86: Make a second write to performance counter if needed |
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On Netburst PMU we need a second write to a performance counter due to cpu erratum.
A simple flag test instead of alternative instructions was choosen because wrmsrl is already a macro and if virtualization is turned on will need an additional wrapper call which is more expencise.
nb: we should propably switch to jump-labels as only this facility reach the mainline.
Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> CC: Robert Richter <robert.richter@amd.com> CC: Peter Zijlstra <peterz@infradead.org> CC: Lin Ming <ming.m.lin@intel.com> CC: Arnaldo Carvalho de Melo <acme@redhat.com> CC: Frédéric Weisbecker <fweisbec@gmail.com> --- arch/x86/kernel/cpu/perf_event.c | 10 ++++++++++ arch/x86/kernel/cpu/perf_event_p4.c | 9 +++++++++ 2 files changed, 19 insertions(+)
Index: linux-2.6.git/arch/x86/kernel/cpu/perf_event.c ===================================================================== --- linux-2.6.git.orig/arch/x86/kernel/cpu/perf_event.c +++ linux-2.6.git/arch/x86/kernel/cpu/perf_event.c @@ -220,6 +220,7 @@ struct x86_pmu { struct perf_event *event); struct event_constraint *event_constraints; void (*quirks)(void); + int perfctr_second_write; int (*cpu_prepare)(int cpu); void (*cpu_starting)(int cpu); @@ -926,6 +927,15 @@ x86_perf_event_set_period(struct perf_ev atomic64_set(&hwc->prev_count, (u64)-left); wrmsrl(hwc->event_base + idx, + (u64)(-left) & x86_pmu.cntval_mask); + + /* + * Due to erratum on certan cpu we need + * a second write to be sure the register + * is updated properly + */ + if (x86_pmu.perfctr_second_write) + wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask); perf_event_update_userpage(event); Index: linux-2.6.git/arch/x86/kernel/cpu/perf_event_p4.c ===================================================================== --- linux-2.6.git.orig/arch/x86/kernel/cpu/perf_event_p4.c +++ linux-2.6.git/arch/x86/kernel/cpu/perf_event_p4.c @@ -829,6 +829,15 @@ static __initconst const struct x86_pmu .max_period = (1ULL << 39) - 1, .hw_config = p4_hw_config, .schedule_events = p4_pmu_schedule_events, + /* + * This handles erratum N15 in intel doc 249199-029, + * the counter may not be updated correctly on write + * so we need a second write operation to do the trick + * (the official workaround didn't work) + * + * the former idea is taken from OProfile code + */ + .perfctr_second_write = 1, }; static __init int p4_pmu_init(void) -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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