Messages in this thread | | | Date | Wed, 26 May 2010 10:41:43 -0700 (PDT) | From | Dan Magenheimer <> | Subject | tsc reliability for Intel Core 2 Duo "Conroe" |
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Looking through code following up on the separate TSC-related thread, I noticed that my Intel Core 2 Duo "Conroe" box is determined to have an unstable TSC, so falls back to clocksource==hpet.
While a Conroe has X86_FEATURE_CONSTANT_TSC and not X86_FEATURE_NONSTOP_TSC, a Conroe is only able to enter C0 and C1 (unlike its sister Intel Core 2 Duo processor "Merom" which can enter C0-C3).
I was under the impression (possibly from an earlier kernel version?) that tsc_constant PLUS inability to enter deep-C states would result in an acceptably stable TSC to use as a clocksource (assuming it passes a TSC warp test).
So is this a bug? Or is my impression incorrect?
See tsc_check_state() in drivers/acpi/processor_idle.c. I can submit a patch, but wanted to check first.
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