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    Subject[21/34] x86, amd: Check X86_FEATURE_OSVW bit before accessing OSVW MSRs
    2.6.34-stable review patch.  If anyone has any objections, please let us know.

    ------------------
    From: Andreas Herrmann <herrmann.der.user@googlemail.com>

    commit f01487119dda3d9f58c9729c7361ecc50a61c188 upstream.

    If host CPU is exposed to a guest the OSVW MSRs are not guaranteed
    to be present and a GP fault occurs. Thus checking the feature flag is
    essential.

    Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
    LKML-Reference: <20100427101348.GC4489@alberich.amd.com>
    Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

    ---
    arch/x86/kernel/process.c | 12 +++++++-----
    1 file changed, 7 insertions(+), 5 deletions(-)
    --- a/arch/x86/kernel/process.c
    +++ b/arch/x86/kernel/process.c
    @@ -459,11 +459,13 @@ static int __cpuinit check_c1e_idle(cons
    * check OSVW bit for CPUs that are not affected
    * by erratum #400
    */
    - rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
    - if (val >= 2) {
    - rdmsrl(MSR_AMD64_OSVW_STATUS, val);
    - if (!(val & BIT(1)))
    - goto no_c1e_idle;
    + if (cpu_has(c, X86_FEATURE_OSVW)) {
    + rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
    + if (val >= 2) {
    + rdmsrl(MSR_AMD64_OSVW_STATUS, val);
    + if (!(val & BIT(1)))
    + goto no_c1e_idle;
    + }
    }
    return 1;
    }



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