Messages in this thread | | | Date | Wed, 12 May 2010 12:36:58 +0200 | From | Johannes Weiner <> | Subject | Re: [LKML] Re: [PATCH v3] ad7877: keep dma rx buffers in seperate cache lines |
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On Wed, May 12, 2010 at 12:35:45AM -0400, Mike Frysinger wrote: > On Tue, May 11, 2010 at 23:23, FUJITA Tomonori wrote: > > Seems that kmalloc is not cacheline aligned on some architectures but > > they works. Probably, we might be just lucky because in general they > > allocate larger buffers than 64 for DMA via kmalloc and the buffers > > are aligned on the size? > > i think the magic combo is: > - DMA buffer is written to (receive)
Check.
> - some driver state is in the same cacheline as the DMA buffer > - that driver state is used after the flush but before the DMA finishes
The kmalloc caches are system-wide. Any other kmalloc(samesize) user could interfer when touching its object between dma_map_single() on the neighbor object and the end of the transfer.
> - only on arches that need software cache coherency > > so i could see this not being an obvious issue for many people > -mike
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