Messages in this thread | | | Date | Wed, 12 May 2010 09:55:48 -0700 | From | "H. Peter Anvin" <> | Subject | Re: [PATCH v3 0/10] Uprobes v3 |
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On 05/12/2010 07:46 AM, Mathieu Desnoyers wrote: > > Now the tricky case is the sequence: instruction A -> int3 -> instruction B, > because a core can only see "instruction A -> instruction B" without any > core synchronization whatsoever, and may not see the int3. That's where the > djprobes logic (with IPIs to all cores) comes into play. But as long as we stick > to "insn A -> int3 -> insn A", things can be done very simply. > > By the way, kprobes rely on the assumption that it is OK to put a breakpoint > atomically and to put back the original instruction afterward. >
Keep in mind the following corner case, though:
insnA -> int3@A -> insnA insnB -> int3@B -> insnB
It is now possible for the core to hit int3@A, without the int3@B being there. The int3 handler *has* to be able to handle any of the int3's put in place, quite possibly out of order, until a core serialization is performed.
-hpa
-- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf.
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