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    SubjectRE: [LKML] Re: [PATCH v3] ad7877: keep dma rx buffers in seperate cache lines
    Mike Frysinger wrote:
    > lets look at the cacheline sizes for arches that dont set
    > ARCH_KMALLOC_MINALIGN to L1_CACHE_BYTES:
    > - alplha - 32 or 64
    > - frv - 32 or 64
    > - blackfin - 32
    > - parisc - 32 or 64
    > - mn10300 - 16
    > - s390 - 256
    > - score - 16
    > - sparc - 32
    > - xtensa - 16 or 32
    >
    > assuming alpha and s390 handle cache coherency in hardware, it looks
    > to me like the proposed assumption (kmalloc returns cachealigned
    > pointers when cache management is in software) does not hold true.
    >
    > so should these other arches also be setting ARCH_KMALLOC_MINALIGN to
    > L1_CACHE_BYTES ?

    IMHO, yes. It just makes sense to avoid false-sharing issues, not to
    allocate unrelated blocks in the same cache line.

    Also as it turns out (hope he doesn't me telling), Christian Zankel
    recently found a bug that was fixed exactly that way, by setting
    ARCH_KMALLOC_MINALIGN to L1_CACHE_BYTES for the Xtensa architecture.
    (Too recent to have percolated to mainline.)

    A lot of the above might be cache line aligned (?).

    -Marc


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