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    SubjectRe: [PATCH 4/5] kgdb: Use atomic operators which use barriers

    > > Russell had this thread:
    > >
    > Russell is wrong.
    > Yes, originally it was about P4's overheating. But let me repeat: the fact
    > is, this _is_ valid kernel code:
    > kernel/sched.c- while (task_is_waking(p))
    > kernel/sched.c: cpu_relax();

    And this is valid (but ugly and not optimal) kernel code:

    kernel/sched.c- while (task_is_waking(p))
    kernel/sched.c: asm volatile("" :: "memory");

    > (where that "task_is_waking()" is simply doing two regular reads, and
    > expects another CPU to be changing them).
    > This has _nothing_ to do with memory barriers, or with overheating.
    > All that matters is that the above kind of while loop must work. The
    > architecture needs to do whatever it needs to do to make it work. End of
    > discussion. If on ARM6 that means "smp_mb()", then that's an ARM6
    > implementation issue. I don't think inserting smp_mb() into cpu_relax() and udelay()
    and similar can ever fix the problem fully.

    Run smp_mb() from periodic interrupt?
    (cesky, pictures)

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      Last update: 2010-04-05 11:23    [W:0.020 / U:83.504 seconds]
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