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Subject[PATCH 08/12] perf, x86: modify some code to allow the introduction of ibs events
Date
The changes are needed to introduce ibs events that are implemented as
special x86 events.

Signed-off-by: Robert Richter <robert.richter@amd.com>
---
arch/x86/kernel/cpu/perf_event.c | 18 +++++++++---------
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 2a7c2fc..67b99a9 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -281,7 +281,7 @@ x86_perf_event_update(struct perf_event *event)
int idx = hwc->idx;
s64 delta;

- if (idx == X86_PMC_IDX_SPECIAL_BTS)
+ if (idx >= X86_PMC_IDX_SPECIAL)
return 0;

/*
@@ -758,10 +758,10 @@ static inline void x86_assign_hw_event(struct perf_event *event,
hwc->last_cpu = smp_processor_id();
hwc->last_tag = ++cpuc->tags[i];

- if (hwc->idx == X86_PMC_IDX_SPECIAL_BTS) {
- hwc->config_base = 0;
- hwc->event_base = 0;
- } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
+ if (hwc->idx < X86_PMC_IDX_FIXED) {
+ hwc->config_base = x86_pmu.eventsel;
+ hwc->event_base = x86_pmu.perfctr;
+ } else if (hwc->idx < X86_PMC_IDX_SPECIAL) {
hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
/*
* We set it so that event_base + idx in wrmsr/rdmsr maps to
@@ -769,9 +769,9 @@ static inline void x86_assign_hw_event(struct perf_event *event,
*/
hwc->event_base =
MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
- } else {
- hwc->config_base = x86_pmu.eventsel;
- hwc->event_base = x86_pmu.perfctr;
+ } else if (hwc->idx == X86_PMC_IDX_SPECIAL_BTS) {
+ hwc->config_base = 0;
+ hwc->event_base = 0;
}
}

@@ -874,7 +874,7 @@ x86_perf_event_set_period(struct perf_event *event)
s64 period = hwc->sample_period;
int ret = 0, idx = hwc->idx;

- if (idx == X86_PMC_IDX_SPECIAL_BTS)
+ if (idx >= X86_PMC_IDX_SPECIAL_BTS)
return 0;

/*
--
1.7.0.3



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