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    SubjectRe: USB mass storage and ARM cache coherency
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    On Sat, 2010-03-06 at 19:36 +0000, Russell King - ARM Linux wrote:
    > On Sat, Mar 06, 2010 at 04:17:23PM +0530, James Bottomley wrote:
    > > On a fault in of exec data, we first try to get the page out of the page
    > > cache. If it's not present, we put the faulting process to sleep and
    > > fetch it in from storage. When we do the read, on the PIO path, the
    > > kernel alias for the page becomes dirty. Some time later, we place the
    > > page into the user space (updating the pte entry that caused a fault).
    > > At this point, we'll call both flush_icache_page() and
    > > update_mmu_cache() ... this is where the I/D resolution should be done.
    >
    > No - this is where things get extremely icky.
    >
    > The problem at this point occurs on SMP architectures. As soon as you
    > update the PTE entry, it is visible to other threads of the application.
    > If you do I-cache handling after updating the PTE, then there is a window
    > where another CPU can execute the page:
    >
    > CPU0 CPU1
    > speculatively prefetches from page N via kernel
    > mapping, loads garbage into I-cache
    > attempts to execute P
    > page fault
    > page N allocated
    > set_pte_at
    > executes P
    > *splat*
    > flush I-cache

    You have two choices - either invalidate the I-cache before the user pte
    becomes visible or set the page as not-executable in set_pte_at() and
    later mark it as executable in update_mmu_cache (via set_pte_ext).

    We currently invalidate the whole I-cache for historical reasons but we
    could actually only invalidate a single page. Since even on latest ARM
    CPUs, the I-cache is a real VIPT (i.e. can have aliases), we would need
    to invalidate on the user mapping (or create a temporary one). The
    latter approach of clearing the X bit in set_pte_at may actually help
    with this scenario (I haven't done any tests though).

    --
    Catalin



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