Messages in this thread | | | Subject | Re: [RFC][PATCH 08/11] perf, x86: Implement simple LBR support | From | Peter Zijlstra <> | Date | Thu, 04 Mar 2010 09:58:06 +0100 |
| |
On Wed, 2010-03-03 at 22:52 +0100, Stephane Eranian wrote: > On Wed, Mar 3, 2010 at 5:39 PM, Peter Zijlstra <a.p.zijlstra@chello.nl> wrote: > > Implement support for Intel LBR stacks that support > > FREEZE_LBRS_ON_PMI. We do not (yet?) support the LBR config register > > because that is SMT wide and would also put undue restraints on the > > PEBS users. > > > You're saying PEBS users have priorities over pure LBR users? > Why is that?
I say no such thing, I only say it would make scheduling the PEBS things more interesting.
> Without coding this, how would you expose LBR configuration to userland > given you're using the PERF_SAMPLE_BRANCH_STACK approach?
Possibly using a second config word in the attr, but given how sucky the hardware currently is (sharing the config between SMT) I'd be inclined to pretend it doesn't exist for the moment.
| |