[lkml]   [2010]   [Mar]   [4]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
    SubjectRe: USB mass storage and ARM cache coherency
    On Thu, 2010-03-04 at 19:51 +0530, James Bottomley wrote:
    > Technically, he is. In the old days, most VI architectures were high
    > end enough not to require PIO transfers. The only exception was an
    > IDE driver used by sparc, which lead to the arch specific ide in/out
    > string instructions, in which sparc actually did all the necessary
    > flushing.

    Actually, Catalin's problem is with newer PIPT ARM :-)

    > So no other drivers than old IDE grew up with cache flushing in the
    > PIO case (and almost no high end VI hardware had an IDE interface, so
    > they rarely got implemented in the arch layer). However, recently,
    > with the transition from old IDE to libata and the prevalence of ARM
    > with more commodity hardware, the deficiency is becoming exposed.
    > Even the PA8000 workstations now come with an IDE CD, which means
    > we're starting to have problems with them as well.

    I don't think there's a core or driver problem in this specific case. As
    we discussed earlier, I believe the problem is that ARM considers a
    fresh page out of the page cache as "clean" instead of "dirty", and
    inverting that like we do on powerpc will fix their problem too.

    > > Seems like ARM has requirement other architectures do not, that is
    > > a) not documented anywhere
    > > b) causes problems
    > >
    > > You could argue that performance improvement (how big is it,
    > anyway?)
    > > is worth it, but this should be agreed to by wider community...
    > Performance is always worth it provided we don't sacrifice
    > correctness.
    > The thing which was discovered in this thread is basically that ARM is
    > handling deferred flushing (for D/I coherency) in a slightly different
    > way from everyone else ... once that's fixed, ARM will likely not have
    > the D/I problem, but we'll still have the libata (and other PIO
    > systems) D flushing issue.

    You mean older VIVT ARM will grow a new issue there ?


     \ /
      Last update: 2010-03-04 22:37    [W:0.021 / U:16.000 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site