Messages in this thread | | | Date | Thu, 04 Mar 2010 11:21:42 -0500 | From | Masami Hiramatsu <> | Subject | Re: [PATCH 09/14] perf, x86: use LBR for PEBS IP+1 fixup |
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Peter Zijlstra wrote: > PEBS always reports the IP+1, that is the instruction after the one > that got sampled, cure this by using the LBR to reliably rewind the > instruction stream. > > CC: Masami Hiramatsu <mhiramat@redhat.com> > CC: Yanmin Zhang <yanmin_zhang@linux.intel.com> > Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> > LKML-Reference: <new-submission> > --- > arch/x86/include/asm/perf_event.h | 19 ++++++ > arch/x86/kernel/cpu/perf_event.c | 70 ++++++++++++------------- > arch/x86/kernel/cpu/perf_event_intel.c | 4 - > arch/x86/kernel/cpu/perf_event_intel_ds.c | 84 +++++++++++++++++++++++++++++- > include/linux/perf_event.h | 6 ++ > 5 files changed, 144 insertions(+), 39 deletions(-) > [...] > Index: linux-2.6/arch/x86/include/asm/perf_event.h > =================================================================== > --- linux-2.6.orig/arch/x86/include/asm/perf_event.h > +++ linux-2.6/arch/x86/include/asm/perf_event.h > @@ -136,6 +136,25 @@ extern void perf_events_lapic_init(void) > > #define PERF_EVENT_INDEX_OFFSET 0 > > +/* > + * Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups. > + * This flag is otherwise unused and ABI specified to be 0, so nobody should > + * care what we do with it. > + */ > +#define PERF_EFLAGS_EXACT (1UL << 3) > + > +#define perf_misc_flags(regs) \ > +({ int misc = 0; \ > + if (user_mode(regs)) \ > + misc |= PERF_RECORD_MISC_USER; \ > + else \ > + misc |= PERF_RECORD_MISC_KERNEL; \ > + if (regs->flags & PERF_EFLAGS_EXACT) \ > + misc |= PERF_RECORD_MISC_EXACT; \ > + misc; }) > + > +#define perf_instruction_pointer(regs) ((regs)->ip)
Hmm, why don't you use instruction_pointer() defined in asm/ptrace.h? And I couldn't find any user of this macro in this patch...
Others looks good to me :)
Thank you,
-- Masami Hiramatsu e-mail: mhiramat@redhat.com
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