lkml.org 
[lkml]   [2010]   [Mar]   [4]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    SubjectRe: USB mass storage and ARM cache coherency
    From
    Date
    On Thu, 2010-03-04 at 14:21 +0000, James Bottomley wrote:
    > The thing which was discovered in this thread is basically that ARM is
    > handling deferred flushing (for D/I coherency) in a slightly different
    > way from everyone else ...

    Doing a grep for PG_dcache_dirty defined in terms of PG_arch_1 reveals
    that MIPS, Parisc, Score, SH and SPARC do similar things to ARM. PowerPC
    and IA-64 use PG_arch_1 as a clean rather than dirty bit.

    --
    Catalin



    \
     
     \ /
      Last update: 2010-03-04 16:31    [W:0.020 / U:1.908 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site