lkml.org 
[lkml]   [2010]   [Mar]   [4]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    SubjectRe: USB mass storage and ARM cache coherency
    From
    Date
    On Thu, 2010-03-04 at 14:27 +0000, Russell King - ARM Linux wrote:
    > On Thu, Mar 04, 2010 at 07:51:52PM +0530, James Bottomley wrote:
    > > On Thu, 2010-03-04 at 14:51 +0100, Pavel Machek wrote:
    > > > Seems like ARM has requirement other architectures do not, that is
    > > > a) not documented anywhere
    > > > b) causes problems
    > > >
    > > > You could argue that performance improvement (how big is it, anyway?)
    > > > is worth it, but this should be agreed to by wider community...
    > >
    > > Performance is always worth it provided we don't sacrifice correctness.
    > > The thing which was discovered in this thread is basically that ARM is
    > > handling deferred flushing (for D/I coherency) in a slightly different
    > > way from everyone else ... once that's fixed, ARM will likely not have
    > > the D/I problem, but we'll still have the libata (and other PIO systems)
    > > D flushing issue.
    >
    > I think you've got that backwards.
    >
    > Reversing the meaning of PG_arch_1 will probably fix the D aliasing issue -
    > since we'll interpret '0' to mean "page is dirty, it needs flushing before
    > hitting userspace", whereas '1' means "page has been cleaned; there are no
    > aliases."
    >
    > This doesn not address the I/D coherency issue, where the Icache needs
    > attention to get rid of speculatively loaded cache lines while old data
    > was present in the cache.

    The I-cache flushing is already handled in update_mmu_cache (or
    set_pte_at in a future patch; I'm not talking about other issues on
    ARM11MPCore here).

    We always invalidate the I-cache currently (since we may have DMA
    transfers and the page's D-cache is clean). As an optimisation, we could
    use PG_arch_2 for I-cache but I don't think there is much performance
    benefit compared to always invalidating the I-cache flushing.

    My understanding from this long discussion is that we cannot get the
    kernel modifying a page cache page which is already mapped in user space
    (well, ptrace does this but we flush the cache there already).

    --
    Catalin



    \
     
     \ /
      Last update: 2010-03-04 16:27    [W:0.022 / U:89.984 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site