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SubjectRe: USB mass storage and ARM cache coherency
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On Wed, 2010-03-03 at 21:54 +0000, Pavel Machek wrote:
> > With some drivers (those doing PIO) or subsystems (SCSI mass storage
> > over USB HCD), there is no call to flush_dcache_page() for page cache
> > pages, hence the ARM implementation of update_mmu_cache() doesn't flush
> > the D-cache (and only invalidating the I-cache doesn't help).
> > The viable solutions so far:
> >
> > 1. Implement a PIO mapping API similar to the DMA API which takes
> > care of the D-cache flushing. This means that PIO drivers would
> > need to be modified to use an API like pio_kmap()/pio_kunmap()
> > before writing to a page cache page.
> > 2. Invert the meaning of PG_arch_1 to denote a clean page. This
> > means that by default newly allocated page cache pages are
> > considered dirty and even if there isn't a call to
> > flush_dcache_page(), update_mmu_cache() would flush the D-cache.
> > This is the PowerPC approach.
>
> What about option
>
> 3. Forget about PG_arch_1 and always do the flush?
>
> How big is the performance impact? Note that current code does not
> even *work* so working, 10% slower code will be an improvement.

The driver fix is as simple as calling a flush_dcache_page() and I've
been carrying such patches in my tree for some time now. The question is
whether we need to do it in the driver or not (would need to update
Documentation/cachetlb.txt as well).

The reason I'm not in favour always doing the flush is that we penalise
DMA drivers where there is no need for extra D-cache flushing (already
handled by the DMA API; option 1 above is similar, just that it is meant
for PIO usage). An ARM patch I proposed for inverting the meaning of
PG_arch_1 also marks a page as clean in the dma_map_* functions.

--
Catalin



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