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    SubjectRe: USB mass storage and ARM cache coherency
    On 02/08/10 10:51, Somebody in the thread at some point said:

    > We could of course flush the caches every time we get a page fault but
    > that's far from optimal, especially since DMA-capable drivers to do not
    > pollute the D-cache and don't need this extra flushing. Note that the
    > recent ARM processors have PIPT caches but separate for I and D and it's
    > the PIO drivers that pollute the D-cache.

    Just noting that AFAIK iMX31 USB and MMC drivers both are PIO at the
    moment, for lack of any platform DMA support of its unusual DMA engine.


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