Messages in this thread | | | Date | Wed, 3 Feb 2010 10:15:45 -0500 (EST) | From | Alan Stern <> | Subject | Re: USB mass storage and ARM cache coherency |
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On Tue, 2 Feb 2010, Andreas Mohr wrote:
> Any ideas? To my uncaring mind this would look like __flush_dcache_page() > not being quite so happy with a NULL pointer that it is being served > (although I haven't managed to precisely investigate yet where the > dereferencing offset 0000041c is coming from). > > Yes, crash is reproducible (three times on boot already, although some bootup > does make it successfully). > > My ehci-q.c has: > > if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { > void *ptr; > for (ptr = urb->transfer_buffer; > ptr < urb->transfer_buffer + urb->transfer_buffer_length; > ptr += PAGE_SIZE) > flush_dcache_page(virt_to_page(ptr)); > } > > Hmm, OTOH this code seems to postulate that urb->transfer_buffer_length > is that 0x41c from above... > (IOW the code is simply missing an urb->transfer_buffer NULL check) > OTOH there would also be the question whether flush_dcache_page() should > have caught the NULL pointer input... > And then there's the question whether urb->transfer_buffer is allowed to end > up as NULL anyway...
Have you looked at the code in qh_urb_transaction() in ehci-q.c involving this_sg_len and buf? It's quite possible that urb->transfer_buffer is a NULL pointer and that the actual buffer is not a contiguous set of pages -- but only if DMA is used.
Alan Stern
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