Messages in this thread Patch in this message | | | Date | Fri, 26 Feb 2010 10:25:54 GMT | From | tip-bot for Peter Zijlstra <> | Subject | [tip:perf/core] perf_events, x86: Remove superflous MSR writes |
| |
Commit-ID: 6667661df4bc76083edf1e08831c20f64429709d Gitweb: http://git.kernel.org/tip/6667661df4bc76083edf1e08831c20f64429709d Author: Peter Zijlstra <a.p.zijlstra@chello.nl> AuthorDate: Wed, 10 Feb 2010 16:10:48 +0100 Committer: Ingo Molnar <mingo@elte.hu> CommitDate: Fri, 26 Feb 2010 10:56:54 +0100
perf_events, x86: Remove superflous MSR writes
We re-program the event control register every time we reset the count, this appears to be superflous, hence remove it.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Arjan van de Ven <arjan@linux.intel.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu> --- arch/x86/kernel/cpu/perf_event.c | 3 --- 1 files changed, 0 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index ad09656..dd09ccc 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -2009,9 +2009,6 @@ static int intel_pmu_save_and_restart(struct perf_event *event) x86_perf_event_update(event, hwc, idx); ret = x86_perf_event_set_period(event, hwc, idx); - if (event->state == PERF_EVENT_STATE_ACTIVE) - intel_pmu_enable_event(hwc, idx); - return ret; }
| |