Messages in this thread | | | Subject | Re: USB mass storage and ARM cache coherency | From | Catalin Marinas <> | Date | Tue, 02 Feb 2010 14:34:14 +0000 |
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On Tue, 2010-02-02 at 13:08 +0000, Oliver Neukum wrote: > Am Dienstag, 2. Februar 2010 13:39:35 schrieb Catalin Marinas: > > > For storage that is correct. But what about other sources of pages, > > > for example iSCSI? > > > > In the iSCSI case, does the HCD driver write directly to a page cache > > page? Or it just fills in network packets that are copied to page cache > > pages by the iSCSI code (sorry, I'm not familiar with this part of the > > kernel). If the latter, the cache flushing in the HCD driver would not > > help and it needs to be done in the iSCSI code. > > As far as I can tell iSCSI does a private copy. But I don't know how > many methods to transfer code pages over USB exist. I'd say the > conservative solution is to flush for everything but control transfers.
flush_dcache_page() is on many architectures implemented lazily so that if the page isn't mapped in user space no flushing takes place. It's mainly the cost of virt_to_page() which I suspect is slightly higher with sparsemem enabled.
-- Catalin
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