Messages in this thread |  | | | Subject | Re: USB mass storage and ARM cache coherency | | From | Catalin Marinas <> | | Date | Tue, 02 Feb 2010 12:01:12 +0000 |
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On Tue, 2010-02-02 at 11:48 +0000, Oliver Neukum wrote: > Am Montag, 1. Februar 2010 18:29:14 schrieb Catalin Marinas: > > + if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) == PIPE_BULK) { > > + void *ptr; > > + for (ptr = urb->transfer_buffer; > > + ptr < urb->transfer_buffer + urb->transfer_buffer_length; > > + ptr += PAGE_SIZE) > > + flush_dcache_page(virt_to_page(ptr)); > Is it correct to limit this to BULK pipes?
I'm not entirely sure. The flush_dcache_page() should only be called for pages that may be mapped into user space (page cache pages). We don't need this for control buffers. It was my impression that what's coming from the mass storage layer intended for page cache pages has the PIPE_BULK type (I may be wrong though).
-- Catalin
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